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e-Article

Low Power Asynchronous Digital Silicon Photomultiplier Based Radiation Detector with On-Chip Photon Counting Buffer.
Document Type
Conference
Source
2022 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC) Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2022 IEEE. :1-5 Nov, 2022
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Nuclear Engineering
Photonics and Electrooptics
Signal Processing and Analysis
Power demand
Scintillators
Radiation detectors
Silicon
System-on-chip
Photonics
Single-photon avalanche diodes
Language
ISSN
2577-0829
Abstract
This paper describes the design and characterization of an asynchronous digital silicon photomultiplier (DSiPM) which employs a novel signal combination strategy and on-board processing to significantly reduce power consumption. The device is a low power (few mW) sensor realized in 180nm complementary metal oxide semiconductor technology with on-chip event capture suitable for direct photon to digital conversion and indirect detection of ionizing radiation in conjunction with a scintillator. The 5x5mm sensor has 256 macro pixels where each macro pixel consists of multiple single photon avalanche photodiode (SPAD) cells and front-end electronics generating digital pulse edges indicating single photon arrivals. The edges from all macro pixels are streamed via a tree architecture to an on-chip synchronous first in – first out (FIFO) buffer counter, where the number of detected photons is summed at a suitable integration time to create a time transient representing the optical output of the scintillator. Division and toggling at each stage of the tree such that individual transitions at higher stages of the tree represent several photons greatly reduces power consumption by reducing the number of transitions propagated across the chip. The data can then be transferred to an external digital processor for identifying the radiation type (gamma or neutron) and source. The on-chip buffer counter is capable of operating up to 100MHz. This novel architecture achieves very low power consumption enabling compact battery-operated applications. The sensor is 3-side tileable, to increase the active area and so match scintillator requirements and has an onboard triggering capability to minimize data transfer rates. Characterization has been performed under continuous and pulsed operation to determine the sensitivity, statistical properties of the output data and power consumption of the device as a function of optical intensity and division factor.