부산대학교 도서관

In the recent years the attention of the semiconductor makers and customers turned to gate oxide robustness on overvoltage, current spikes or ringing effect which could lead to undesirable effects on the performance of powerMOSFET loss of functionality, reliability up to irreversible damage. This is a critical and serious issue related to TrenchFET technologies where local gate oxide thinning is a frequent and common cause of process instability or failure. This publication presents a method to electrically highlight and exacerbate these process weaknesses and at the same time to exploit them to detect lithographic problems related to the definition of source contacts. All this by collecting equivalent if not superior information on an entire wafer map in less time than a precise physical analysis.