부산대학교 도서관

This article presents an efficient buck converter design using the proposed outphase-interleaved hybrid switched-capacitor (OISC) topology. The outphase-interleaved switched-capacitor (SC) cells significantly extend the $C_{\mathrm {F}}$ charge-balancing phase without disturbing the inductor volt-second balance (VSB), while doubling the effective inductor switching frequency for reduced current ripple. As a result, it addresses the intrinsic issue of sharply increased flying capacitor ( $C_{\mathrm {F}}$ ) inrush current in existing SC dual-/multi-path (DP/MP) hybrid buck converters under extreme duty ratios, resolving the tradeoff between SC cell conduction loss and inductor dc current ( $I_{L,\mathrm {dc}}$ ) reduction capability. The proposed topology attains three key advantages: 1) relived $C_{\mathrm {F}}$ hard-charging-induced inrush current; 2) reduced $I_{L,\mathrm {dc}}$ ; and 3) power stage normal operation without relying on an output capacitor $(C_{\mathrm {OUT}})$ , resulting in improved conversion efficiency and power density. To enhance the overall power density and mitigate gate-driving path ringing, we propose an area-efficient fully ON-chip gate-driving scheme with a shared charge pump (CP), ensuring proper operations with all-NMOS power switches. Fabricated in a 180-nm CMOS process with 7.63 mm2 chip area, the converter achieves a peak conversion efficiency of 97.3% and an overall peak current density of 585 mA/mm3 at 90.1% efficiency. Supporting a load current ( $I_{\mathrm {LOAD}}$ ) from 0.05 to 3.1 A, it converts 1.8–3.3 V input to 0.8–1.8 V output. Measured output voltage ( $V_{\mathrm {OUT}}$ ) ripple is ~3.3% of $V_{\mathrm {OUT}}$ dc under 3.1 A $I_{\mathrm {LOAD}}$ with zero $C_{\mathrm {OUT}}$ .