e-Article
A dual core oxide 8T SRAM cell with low Vccmin and dual voltage supplies in 45nm triple gate oxide and multi Vt CMOS for very high performance yet low leakage mobile SoC applications
Document Type
Conference
Author
Source
2010 Symposium on VLSI Technology VLSI Technology (VLSIT), 2010 Symposium on. :135-136 Jun, 2010
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
In this work we have demonstrated, for the first time, a 0.605µm 2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the standby leakage, and lower Vccmin. The PU Vt and dual core oxide boundary were optimized to achieve robust Vccmin, process margin and reliability. The 45LPG thin core transistors and the DCO 8T SRAM are able to achieve 1.5GHz speed with ∼500mW at 0.9V and a low Vccmin of 0.6V.