e-Article
Efficient Architecture for VVC Angular Intra Prediction based on a Hardware-Friendly Heuristic
Document Type
Conference
Source
2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS) Circuits and Systems (LASCAS), 2023 IEEE 14th Latin America Symposium on. :1-4 Feb, 2023
Subject
Language
ISSN
2473-4667
Abstract
This paper presents a low-power and high-performance hardware design for the Angular Intraframe Prediction (AIP) of the Versatile Video Coding (VVC). The designed architecture is based on a proposed heuristic developed to reduce the angular prediction computational effort. The proposed heuristic presented average encoding time reduction of 60.92%, and coding efficiency (BD-Rate) impact of 8.62%. The architecture was synthesized for TSMC 40nm ASIC technology and the results show it can process HD 1080p videos at 30 frames per second, with a power dissipation of 91.6mW. To the best of the author's knowledge, this is the first work in the literature reporting an ASIC design for the VVC AIP.