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| LDR | 00848cam a2200265 c 4500 | ||
| 001 | 0093799095▲ | ||
| 005 | 20180519065816▲ | ||
| 007 | ta▲ | ||
| 008 | 170411s2017 ulka 001c kor ▲ | ||
| 020 | ▼a9791159062292▼g93560 :▼c₩28000▲ | ||
| 035 | ▼a(KERIS)BIB000014493411▲ | ||
| 040 | ▼a211046▼c211046▼d221016▲ | ||
| 082 | 0 | 4 | ▼a621.395▼223▲ |
| 090 | ▼a621.395▼b이58ㄷ2▲ | ||
| 100 | 1 | ▼a이승호▲ | |
| 245 | 2 | 0 | ▼a(ALTERA MAX+PLUS II를 사용한) 디지털 논리회로 설계 :▼bVHDL /▼d이승호,▼e박용수,▼e이주현 共著▲ |
| 250 | ▼a제2판▲ | ||
| 260 | ▼a서울 :▼bD.B.Info,▼c2017▲ | ||
| 300 | ▼a653 p. :▼b삽화 ;▼c26 cm▲ | ||
| 500 | ▼a색인: p. 645-653▲ | ||
| 653 | ▼a디지털논리설계▼a논리회로설계▲ | ||
| 700 | 1 | ▼a박용수▲ | |
| 700 | 1 | ▼a이주현▲ | |
| 940 | ▼a디지털 논리회로 설계 브이에이치디엘▲ | ||
| 999 | ▼a경동욱▼c강설혜▲ |
(ALTERA MAX+PLUS II를 사용한) 디지털 논리회로 설계 :VHDL
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