학술논문
14nm FDSOI technology for high speed and energy efficient applications
Document Type
Conference
Author
Weber, O.; Josse, E.; Andrieu, F.; Cros, A.; Richard, E.; Perreau, P.; Baylac, E.; Degors, N.; Gallon, C.; Perrin, E.; Chhun, S.; Petitprez, E.; Delmedico, S.; Simon, J.; Druais, G.; Lasserre, S.; Mazurier, J.; Guillot, N.; Bernard, E.; Bianchini, R.; Parmigiani, L.; Gerard, X.; Pribat, C.; Gourhant, O.; Abbate, F.; Gaumer, C.; Beugin, V.; Gouraud, P.; Maury, P.; Lagrasta, S.; Barge, D.; Loubet, N.; Beneyton, R.; Benoit, D.; Zoll, S.; Chapon, J.-D.; Babaud, L.; Bidaud, M.; Gregoire, M.; Monget, C.; Le-Gratiet, B.; Brun, P.; Mellier, M.; Pofelski, A.; Clement, L.R.; Bingert, R.; Puget, S.; Kruck, J.-F.; Hoguet, D.; Scheer, P.; Poiroux, T.; Manceau, J.-P.; Rafik, M.; Rideau, D.; Jaud, M.-A.; Lacord, J.; Monsieur, F.; Grenouillet, L.; Vinet, M.; Liu, Q.; Doris, B.; Celik, M.; Fetterolf, S.P.; Faynot, O.; Haond, M.
Source
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. :1-2 Jun, 2014
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.