학술논문
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Document Type
Conference
Author
Loubet, N.; Hook, T.; Montanini, P.; Yeung, C.-W.; Kanakasabapathy, S.; Guillom, M.; Yamashita, T.; Zhang, J.; Miao, X.; Wang, J.; Young, A.; Chao, R.; Kang, M.; Liu, Z.; Fan, S.; Hamieh, B.; Sieg, S.; Mignot, Y.; Xu, W.; Seo, S.-C.; Yoo, J.; Mochizuki, S.; Sankarapandian, M.; Kwon, O.; Carr, A.; Greene, A.; Park, Y.; Frougier, J.; Galatage, R.; Bao, R.; Shearer, J.; Conti, R.; Song, H.; Lee, D.; Kong, D.; Xu, Y.; Arceo, A.; Bi, Z.; Xu, P.; Muthinti, R.; Li, J.; Wong, R.; Brown, D.; Oldiges, P.; Robison, R.; Arnold, J.; Felix, N.; Skordas, S.; Gaudiello, J.; Standaert, T.; Jagannathan, H.; Corliss, D.; Na, M.-H.; Knorr, A.; Wu, T.; Gupta, D.; Lian, S.; Divakaruni, R.; Gow, T.; Labelle, C.; Lee, S.; Paruchuri, V.; Bu, H.; Khare, M.
Source
2017 Symposium on VLSI Technology VLSI Technology, 2017 Symposium on. :T230-T231 Jun, 2017
Subject
Language
ISSN
2158-9682
Abstract
In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.