학술논문
64nm pitch interconnects: Optimized for designability, manufacturability and extendibility
Document Type
Conference
Author
Goldberg, C.; Park, S.H.; Kim, B.Y.; Law, S.B.; Hamieh, B.; Jung, J.; Kim, B.H.; Rhee, S.H.; Oh, M.; Mobley, M.; Laffosse, E.; Kim, A.; Thomas, A.; Malinge, P.; Fryxell, T.; Lim, K.J.; Park, I.S.; Bahierathan, B.; Wu, F.; Erenturk, B.; Jeon, W.C.; Choi, H.C.; Park, Y.J.; Kim, H.; Chen, T.Q.; Thibaut, S.; Niu, C.; Zhang, J.; Filippi, R.; Kaltalioglu, E.; Achanta, R.; Wang, P.-C.; Yang, H.; Geronimi, J.P.; Pagette, F.; Chauhan, V.; Ogino, A.; Srivastava, R.; Koshy, R.; Baumann, F.; Simon, A.; Nag, J.; Cheng, T.; Fitzsimmons, J.; Tseng, W.; Lin, Y.; Sun, Z.; Bolom, T.; Ko, T.-M.; Clevenger, L.; Kim, J; Sudijono, J.; Sampson, R.
Source
2013 Symposium on VLSI Technology VLSI Technology (VLSIT), 2013 Symposium on. :T202-T203 Jun, 2013
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell abutment conflicts. A Self-Aligned-Via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask. Yield ramp rate, groundrule validation, and reliability qualification were each accelerated by early brightfield adoption for trench and via, producing a robust cross-module process window. The resulting groundrules and process module have been “plugged in” to multiple technology nodes without re-development needed (e.g. 20LPM, 14nm FINFET, 14FDSOI, 10nm P&R levels). Scaling, performance, and reliability requirements are achieved across a spectrum of low power-high performance applications.