학술논문
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell
Document Type
Conference
Author
Fenouillet-Beranger, C.; Denorme, S.; Icard, B.; Boeuf, F.; Coignus, J.; Faynot, O.; Brevard, L.; Buj, C.; Soonekindt, C.; Todeschini, J.; Le-Denmat, J.C.; Loubet, N.; Gallon, C.; Perreau, P.; Manakli, S.; Minghetti, B.; Pain, L.; Arnal, V.; Vandooren, A.; Aime, D.; Tosti, L.; Savardi, C.; Broekaart, M.; Gouraud, P.; Leverd, F.; Dejonghe, V.; Brun, P.; Guillermet, M.; Aminpur, M.; Barnola, S.; Rouppert, F.; Martin, F.; Salvetat, T.; Lhostis, S.; Laviron, C.; Auriac, N.; Kormann, T.; Chabanne, G.; Gaillard, S.; Belmont, O.; Laffosse, E.; Barge, D.; Zauner, A.; Tarnowka, A.; Romanjec, K.; Brut, H.; Lagha, A.; Bonnetier, S.; Joly, F.; Mayet, N.; Cathignol, A.; Galpin, D.; Pop, D.; Delsol, R.; Pantel, R.; Pionnier, F.; Thomas, G.; Bensahel, D.; Deleonibus, S.; Skotnicki, T.; Mingam, H.
Source
2007 IEEE International Electron Devices Meeting Electron Devices Meeting, 2007. IEDM 2007. IEEE International. :267-270 Dec, 2007
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good I on /I off performance for nMOS and pMOS transistors in the ultra-low-leakage regime (I off =6.6 pA/μm) are presented. In addition co-integration of high voltage devices with EOT 29A/V dd 1.8 V are made. For the first time, the functionality of 0.248 μm and 0.179 μm 2 6T-SRAM bit-cells is demonstrated on FDSOI technology with a high-k/metal gate stack.