학술논문
3D sequential integration: applications and associated key enabling modules (design & technology)
Document Type
Conference
Author
Batude, P.; Billoint, O.; Thuries, S.; Malinge, P.; Fenouillet-Beranger, C.; Peizerat, A.; Sicard, G.; Vivet, P.; Reboh, S.; Cavalcante, C.; Brunet, L.; Ribotta, M.; Brevard, L.; Garros, X.; Frutuoso, T. Mota; Sklenard, B.; Lacord, J.; Kanyandekwe, J.; Kerdiles, S.; Sideris, P.; Theodorou, C.; Lapras, V.; Mouhdach, M.; Gaudin, G.; Besnard, G.; Radu, I.; Ponthenier, F.; Farcy, A.; Jesse, E.; Guyader, F.; Matheret, T.; Brunet, P.; Milesi, F.; Van-Jodin, L. Le; Sarrazin, A.; Perrin, B.; Moulin, C.; Maitrejean, S.; Alepidis, M.; Ionica, I.; Cristoloveanu, S.; Gaillard, F.; Vinet, M.; Andrieu, F.; Arcamone, J.; Ollier, E.
Source
2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :3.2.1-3.2.4 Dec, 2021
Subject
Language
ISSN
2156-017X
Abstract
3D sequential integration (3DSI) is envisioned for highly miniaturized smart imagers and fine pitch logic and memory imbrication. This paper describes partitioning in 3DSI and design methodologies. A status is also done on low temperature processes and device performance adapted for these applications (i.e. digital $\mathrm{V}_{\text{DD}}\leq 1\mathrm{V}$ and analog $\mathrm{V}_{\text{DD}}\geq 2.5\mathrm{V}$ devices).