학술논문
Folded fully depleted Bulk+ technology as a highly W-scaled planar solution
Document Type
Conference
Author
Bidal, G.; Loubet, N.; Fenouillet-Beranger, C.; Denorme, S.; Perreau, P.; Chanemougame, D.; Laviron, C.; Leverd, F.; Barnola, S.; Beneyton, R.; Duluard, C.; Chapon, J.D.; Gouraud, P.; Salvetat, T.; Grosjean, M.; Deloffre, E.; Fleury, D.; Clement, L.; Pribat, C.; Pantel, R.; Monfray, S.; Dutartre, D.; Ghibaudo, G.; Boeuf, F.; Skotnicki, T.
Source
ESSDERC 2008 - 38th European Solid-State Device Research Conference Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European. :210-213 Sep, 2008
Subject
Language
ISSN
1930-8876
2378-6558
2378-6558
Abstract
This work proposes a Bulk+ planar fully depleted “folded” technology as an innovative cost worthy solution for upcoming low power nodes. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide thin film/thin BOX devices with improved transistor gain β for a given designed footprint W design . We compare the fabrication between 〈110〉 channel, i.e. non-rotated wafer, and 〈100〉 channel, i.e. 45°-rotated wafer, for the same (100) surface orientation.