학술논문
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution
Document Type
Article
Author
Bidal, G.; Loubet, N.; Fenouillet-Beranger, C.; Denorme, S.; Perreau, P.; Fleury, D.; Clement, L.; Laviron, C.; Leverd, F.; Gouraud, P.; Barnola, S.; Beneyton, R.; Torres, A.; Duluard, C.; Chapon, J.D.; Orlando, B.; Salvetat, T.; Grosjean, M.; Deloffre, E.; Pantel, R.; Dutartre, D.; Monfray, S.; Ghibaudo, G.; Boeuf, F.; Skotnicki, T.
Source
In Solid State Electronics 2009 53(7):735-740
Subject
Language
ISSN
0038-1101