학술논문
High performance CMOS FDSOI devices activated at low temperature
Document Type
Conference
Author
Pasini, L.; Batude, P.; Lacord, J.; Casse, M.; Mathieu, B.; Sklenard, B.; Luce, F. Piegas; Micout, J.; Payet, A.; Mazen, F.; Besson, P.; Ghegin, E.; Borrel, J.; Daubriac, R.; Hutin, L.; Blachier, D.; Barge, D.; Chhun, S.; Mazzocchi, V.; Cros, A.; Barnes, J-P.; Saghi, Z.; Delaye, V.; Rambal, N.; Lapras, V.; Mazurier, J.; Weber, O.; Andrieu, F.; Brunet, L.; Fenouillet-Beranger, C.; Rafhay, Q.; Ghibaudo, G.; Cristiano, F.; Haond, M.; Boeuf, F.; Vinet, M.
Source
2016 IEEE Symposium on VLSI Technology VLSI Technology, 2016 IEEE Symposium on. :1-2 Jun, 2016
Subject
Language
ISSN
2158-9682
Abstract
3D sequential integration requires top FETs processed with a low thermal budget (500–600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).