학술논문
Recent advances in low temperature process in view of 3D VLSI integration
Document Type
Conference
Author
Fenouillet-Beranger, C.; Batude, P.; Brunet, L.; Mazzocchi, V.; Lu, C-M.V.; Deprat, F.; Micout, J.; Samson, M-P.; Previtali, B.; Besombes, P.; Rambal, N.; Lapras, V.; Andrieu, F.; Billoint, O.; Brocard, M.; Thuries, S.; Cibrario, G.; Acosta-Alba, P.; Mathieu, B.; Kerdiles, S.; Nemouchi, F.; Arvet, C.; Besson, P.; Loup, V.; Gassilloud, R.; Garros, X.; Leroux, C.; Beugin, V.; Guerin, C.; Benoit, D.; Pasini, L.; Hartmann, J-M.; Vinet, M.
Source
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016 IEEE. :1-3 Oct, 2016
Subject
Language
Abstract
In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.