부산대학교 도서관

Technological advancements in multi-die, chiplet, or other 3D architecture design are required to fulfill the high computational power needed for chips in the AI/meta world. Computing demands require die scaling, which can be achieved by fabrication of chips with chiplets integration in 3D. However, 3DICs designs requires new method and considerations for functional and test hardware access. This paper describes the hierarchical approach for DFT access of logic and memory dies through an IEEE 1838 compliant interface. This paper will introduce methodology to realize a stacked IC involving a) configuration and insertion of DFT at RTL, b) synthesis and fault list generation for TSV testing and other die-to-die connections, and c) test pattern porting for die-level test programs to the package pins.