학술논문
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-nand Technology and Featuring a 23.3 Gb/mm2 Bit Density
Document Type
Periodical
Author
Khakifirooz, A.; Anaya, E.; Balasubrahmanyam, S.; Bennett, G.; Castro, D.; Egler, J.; Fan, K.; Ferdous, R.; Ganapathi, K.; Guzman, O.; Ha, C.W.; Haque, R.; Harish, V.; Jalalifar, M.; Jungroth, O.W.; Kang, S.; Karbasian, G.; Kim, J.; Li, S.; Madraswala, A.S.; Maddukuri, S.; Mohammed, A.; Mookiah, S.; Nagabhushan, S.; Ngo, B.; Patel, D.; Poosarla, S.K.; Prabhu, N.V.; Quiroga, C.; Rajwade, S.; Rahman, A.; Shah, J.; Shenoy, R.S.; Menson, E.T.; Tankasala, A.; Thirumala, S.K.; Upadhyay, S.; Upadhyayula, K.; Velasco, A.; Vemula, N.K.B.; Venkataramaiah, B.; Zhou, J.; Pathak, B.M.; Kalavade, P.
Source
IEEE Solid-State Circuits Letters IEEE Solid-State Circuits Lett. Solid-State Circuits Letters, IEEE. 6:161-164 2023
Subject
Language
ISSN
2573-9603
Abstract
We present the industry’s first 5b/cell (PLC) NAND chip, fabricated in a 192-layer floating-gate (FG) technology. With a die capacity of 1.67 Tb and an area of 73.3 mm 2 , it delivers a record bit density of 23.3 Gb/mm 2 . Key innovations to enable reliable PLC operation and the features implemented to support system-level usage are described. These include: a fast soft-bit read algorithm capable of handling the presence of defective bitlines; a fast read-calibration algorithm; a reverse-read waveform to improve the read margin; SLC-write-through; and program suspend and resume algorithm compatible with the above read operations.