학술논문
Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric
Document Type
Conference
Author
Aime, D.; Fenouillet-Beranger, C.; Perreau, P.; Denorme, S.; Coignus, J.; Cros, A.; Fleury, D.; Faynot, O.; Vandooren, A.; Gassilloud, R.; Martin, F.; Barnola, S.; Salvetat, T.; Chabanne, G.; Brevard, L.; Aminpur, M.; Leverd, F.; Gwoziecki, R.; Boeuf, F.; Hobbs, C.; Zauner, A.; Muller, M.; Cosnier, V.; Minoret, S.; Bensahel, D.; Orlowski, M.; Mingam, H.; Wild, A.; Deleonibus, S.; Skotnicki, T.
Source
ESSDERC 2007 - 37th European Solid State Device Research Conference Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European. :255-258 Sep, 2007
Subject
Language
ISSN
1930-8876
2378-6558
2378-6558
Abstract
This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TIN midgap metal gate.