학술논문
0.248/spl mu/m/sup 2/ and 0.334/spl mu/m/sup 2/ conventional bulk 6T-SRAM bit-cells for 45nm node low cost - general purpose applications
Document Type
Conference
Author
Boeuf, F.; Arnaud, F.; Boccaccio, C.; Salvetti, F.; Todeschini, J.; Pain, L.; Jurdit, M.; Manakli, S.; Icard, B.; Planes, N.; Gierczynski, N.; Denorme, S.; Borot, B.; Ortolland, C.; Duriez, B.; Tavel, B.; Gouraud, P.; Broekaart, M.; Dejonghe, V.; Brun, P.; Guyader, F.; Morini, P.; Reddy, C.; Aminpur, M.; Laviron, C.; Smith, S.; Jacquemin, J.P.; Mellier, M.; Andre, F.; Bicais-Lepinay, N.; Jullian, S.; Bustos, J.; Skotnicki, T.
Source
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. VLSI Technology VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on. :130-131 2005
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
This work highlights the realization and 0.248/spl mu/m/sup 2/ to 0.334/spl mu/m/sup 2/ SRAM bit-cells with conventional bulk technology based on 19/spl Aring/ CET SiON gate oxide, poly-silicon gate electrode, and mobility enhancement techniques for both nMOS and pMOS. High density critical lithography levels have been exposed with e-beam direct writing thus contributing to the overall cost-effectiveness of the technology.