학술논문
Low cost 65nm CMOS platform for Low Power & General Purpose applications
Document Type
Conference
Author
Arnaud, F.; Duriez, B.; Tavel, B.; Pain, L.; Todeschini, J.; Jurdit, M.; Laplanche, Y.; Boeuf, F.; Salvetti, F.; Lenoble, D.; Reynard, J.P.; Wacquant, F.; Morin, P.; Emonet, N.; Barge, D.; Bidaud, M.; Ceccarelli, D.; Vannier, P.; Loquet, Y.; Leninger, H.; Judong, F.; Perrot, C.; Guilmeau, I.; Palla, R.; Beverina, A.; DeJonghe, V.; Broekaart, M.; Vachellerie, V.; Bianchi, R.A.; Borot, B.; Devoivre, T.; Bicais, N.; Roy, D.; Denais, M.; Rochereau, K.; Difrenza, R.; Planes, N.; Brut, H.; Vishnobulta, L.; Reber, D.; Stolk, P.; Woo, M.
Source
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. VLSI technology VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on. :10-11 2004
Subject
Language
Abstract
A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 /spl mu/m/sup 2/ bit-cells with 240mV of SNM and 35 /spl mu/A of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 /spl mu/A/ /spl mu/m and 400 /spl mu/A/ /spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/ = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. /spl mu/m) and analog voltage gain factor (G/sub m//G/sub d/>2000 for L = 10 /spl mu/m) at the leading edge for this process technology. NBTI criteria at 125/spl deg/C for both LP and GP transistors are presented and characterized at overdrive conditions.