학술논문
A Generic Trap Generation Framework for MOSFET Reliability—Part I: Gate Only Stress–BTI, SILC, and TDDB
Document Type
Periodical
Author
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 71(1):114-125 Jan, 2024
Subject
Language
ISSN
0018-9383
1557-9646
1557-9646
Abstract
The Reaction-Diffusion-Drift model is validated as a trap generation framework during Bias Temperature Instability (BTI), Stress Induced Leakage Current (SILC), and Time Dependent Dielectric Breakdown (TDDB) experiments. The model is implemented in standalone and Technology CAD (TCAD)-based deterministic and standalone stochastic versions. Different implementations show equivalence of the time kinetics of trap generation during stress and trap passivation after stress. The trigger for different type of experiments is introduced via a single reaction parameter. The model is validated against measured data under diverse experimental conditions, either solely, or along with other models to account for additional physical processes. A circuit simulation platform that uses the physical trap generation model is utilized to estimate activity aware aging in logic circuits due to BTI. The error associated with effective AC duty simulation is shown. Implementation and validation for the Hot Carrier Degradation (HCD) is presented in part-II of this article.