학술논문
Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect
Document Type
Conference
Author
Demolliens, O.; Berruyer, P.; Morand, Y.; Tabone, C.; Roman, A.; Cochet, M.; Assous, M.; Feldis, H.; Blanc, R.; Tabouret, E.; Louis, D.; Arvet, C.; Lajoinie, E.; Gobil, Y.; Passemard, G.; Jourdan, F.; Moussavi, M.; Cordeau, M.; Morel, T.; Mourier, T.; Ulmer, L.; Sicurani, E.; Tardif, F.; Beverina, A.; Trouillet, Y.; Renaud, D.
Source
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247) Interconnect technology Interconnect Technology, 1999. IEEE International Conference. :198-199 1999
Subject
Language
Abstract
This paper describes the integration of copper and SilK in a 0.18 /spl mu/m DLM interconnect. The main integration issues such as dual damascene patterning, SilK porosity and copper filling have been addressed, as shown by the 0.5 /spl Omega/-100% yield obtained for 0.3 /spl mu/m vias. The Cu/SilK interest is confirmed by a 40% RC reduction compared to a Cu-SiO/sub 2/ structure.