학술논문
Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Device Contacts
Document Type
Conference
Author
Radosavljevic, Marko; Huang, C.-Y.; Galatage, R.; Qayyum, M. F.; Wiedemer, J. A.; Clinton, E.; Bennett, D.; Ryu, H.; Thomas, N. K.; Morrow, P.; Michaelos, T.; Nahm, R.; Briggs, N.; Roy, A.; Kuo, C. C.; Atanasov, S.; Ghose, S.; Zussblatt, N.; Kumar, N.; Unluer, D.; Beasley, M.; Tan, J. M.; Tan, L. H.; Elkins, M.; Cekli, S.; Hermann, R.; Shoer, L.; El Qader, M. Abd; Desai, U.; Edwards, T.; Prasad, P.; Armstrong, J.; Ghosh, M.; Liao, Y.-A.; Kapinus, V.; Dixit, D.; Harper, M. K.; Tran, P.; Cheong, K. L.; Fatehi, A.; Oni, A. A.; Franco, N.; Krist, B. J.; Metz, M. V.; Dewey, G.; Schenker, R.; Kobrinsky, M. J.
Source
2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023
Subject
Language
ISSN
2156-017X
Abstract
A device architecture with n-MOS and p-MOS transistors stacked on top of each other is considered a key option to continue scaling in the semiconductor industry. We report experimental demonstrations of gate-all-around based 3D stacked CMOS devices at scaled gate pitch down to 60nm. Our most scaled devices consist of 3 n-MOS on top of 3 p-MOS nanoribbons with 30nm vertical separation, vertically stacked dual-source/drain epitaxy and dual metal workfunction gate stacks. In addition, we demonstrate a vertical nanoribbon depopulation process, potentially enabling the implementation of complex circuit functions where the number of n-MOS and p-MOS devices are not equal. Finally, by combining 3D stacked CMOS devices with backside power via and direct backside device contacts (BSCON), we demonstrate for the first time fully functional scaled inverters down to contacted poly pitch (CPP) of 60nm.