학술논문
Dual phase TOSI-gate process on High-K dielectrics in a CMP-less flow
Document Type
Conference
Author
Source
2006 European Solid-State Device Research Conference Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European. :117-120 Sep, 2006
Subject
Language
ISSN
1930-8876
2378-6558
2378-6558
Abstract
In this paper, we demonstrate for the first time a new original approach of the integration of dual phase TOtally Silicided (TOSI) Gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni2Si for the PMOS gate electrode on High-K dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function dota. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-K gate oxides.