학술논문
CMP-less integration of 40nm-gate totally silicided (TOSI) bulk transistors using selective S/D Si epitaxy and ultra-low gates
Document Type
Conference
Author
Source
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Solid-State Device Research Conference Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European. :453-456 2005
Subject
Language
ISSN
1930-8876
2378-6558
2378-6558
Abstract
In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain a well-behaved silicidation of the junctions and the full gate within one single step with minimal gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.