학술논문
High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration
Document Type
Conference
Author
Micout, J.; Lapras, V.; Batude, P.; Fenouillet-Beranger, C.; Lacord, J.; Sklenard, B.; Mathieu, B.; Rafhay, Q.; Mazzocchi, V.; Colinge, J.-P.; Lachal, L.; Garros, X.; Casse, M.; Toffoli, A.; Romano, G.; Allain, F.; Brunet, L.; Hartmann, J.-M.; Bortolin, R.; Mazen, F.; Barraud, S.; Rambal, N.; Tabone, C.; Samson, M.-P.; Besombes, P.; Delaye, V.; Saghi, Z.; Loup, V.; Comboroure, C.; Balan, V.; Desvoivres, L.; Vizioz, C.; Ghibaudo, G.; Vinet, M.
Source
2017 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2017 IEEE International. :32.2.1-32.2.4 Dec, 2017
Subject
Language
ISSN
2156-017X
Abstract
For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.