학술논문
Gate stack optimization for 65 nm CMOS low power and high performance platform
Document Type
Conference
Author
Source
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. Electron devices meeting Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. :847-850 2004
Subject
Language
Abstract
This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We obtained a large carrier mobility enhancement for both NMOS (+50%) and PMOS (+20%) thanks to an important biaxial tensile stress generated by Ge predoping. Very simple and epitaxy-free, this architecture is directly compatible with both low power and high performance transistors. Competitive IonN = 1000/spl mu/A//spl mu/m and IonP = 400/spl mu/A//spl mu/m were found for Ioff = 100nA//spl mu/m at IV Vdd operation. Attractive matching factor A/sub VT/ lower than 2.5 mV/spl middot//spl mu/m has been obtained with poly grain size optimization. NBTI criteria have been successfully achieved thanks to a complementary Fluorine implant inside the P+ gate.