학술논문
A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform
Document Type
Conference
Author
Arnaud, F.; Boeuf, F.; Salvetti, F.; Lenoble, D.; Wacquant, F.; Regnier, C.; Morin, P.; Emonet, N.; Denis, E.; Oberlin, J.C.; Ceccarelli, D.; Vannier, P.; Imbert, G.; Sicard, A.; Perrot, C.; Belmont, O.; Guilmeau, I.; Sassoulas, P.O.; Delmedico, S.; Palla, R.; Leverd, F.; Beverina, A.; DeJonghe, V.; Broekaart, M.; Pain, L.; Todeschini, J.; Charpin, M.; Laplanche, Y.; Neira, D.; Vachellerie, V.; Borot, B.; Devoivre, T.; Bicais, N.; Hinschberger, B.; Pantel, R.; Revil, N.; Parthasarathy, C.; Planes, N.; Brut, H.; Farkas, J.; Uginet, J.; Stolk, P.; Woo, M.
Source
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) VLSI technology VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on. :65-66 2003
Subject
Language
Abstract
This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at V/sub dd/=0.9 Volt using a conventional nitrided gate oxide dielectric. A comparison between offset spacer and PLAsma Doping (PLAD) is made for the transistor characteristics with very promising V/sub th/-L/sub d/ and V/sub th/-W/sub d/ profiles measured. Lithography employed a combination of both optical lithography and e-beam imaging. The BEOL integration used a conventional low K dielectric with copper metallization.