학술논문
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products
Document Type
Conference
Author
Jan, C.-H.; Al-amoody, F.; Chang, H.-Y.; Chang, T.; Chen, Y.-W.; Dias, N.; Hafez, W.; Ingerly, D.; Jang, M.; Karl, E.; Shi, S. K.-Y.; Komeyli, K.; Kilambi, H.; Kumar, A.; Byon, K.; Lee, C.-G.; Lee, J.; Leo, T.; Liu, P.-C.; Nidhi, N.; Olac-vaw, R.; Petersburg, C.; Phoa, K.; Prasad, C.; Quincy, C.; Ramaswamy, R.; Rana, T.; Rockford, L.; Subramaniam, A.; Tsai, C.; Vandervoorn, P.; Yang, L.; Zainuddin, A.; Bai, P.
Source
2015 Symposium on VLSI Circuits (VLSI Circuits) VLSI Circuits (VLSI Circuits), 2015 Symposium on. :T12-T13 Jun, 2015
Subject
Language
ISSN
2158-5601
2158-5636
2158-5636
Abstract
A leading edge 14 nm SoC platform technology based upon the 2 nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um 2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.