부산대학교 도서관

Traditional 2-D SRAM scaling has been slowing down and suffers from high parasitic resistance of critical signals like wordline (WL) and bitline (BL). As 3-D technologies such as hybrid wafer bonding (HWB) mature, increasingly finer pitches of 3-D interconnects are possible, enabling the possibility of 3-D partitioned memory designs. 3-D-split SRAMs, realized by splitting or folding an SRAM macro across two or more die stacks, may reduce the delay and power incurred inside the macro by mitigating the BL or WL signal RC parasitics. However, the efficacy of such a 3-D-split SRAM would depend on the parasitic overhead of the inter-tier 3-D back-end-of-line (3-D-BEOL) interconnects. We perform an early exploration of the BEOL options in the context of HWB and propose two separate approaches for optimizing the BEOL for 3-D-split SRAM designs. Measured results from 12 nm FinFET 64 kb prototype SRAM macros, designed in 2-D, but configured to capture the parasitic effects of 3-D-BEOL interconnects, indicate that 3-D-split SRAMs can provide 110–127 mV lower ${V} _{\text {MIN}}$ or 9%–14% faster access time, equivalent to the gains achieved with one full process node dimensional scaling.