학술논문
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper
Document Type
Conference
Author
Greene, B.; Liang, Q.; Amarnath, K.; Wang, Y.; Schaeffer, J.; Cai, M.; Liang, Y.; Saroop, S.; Cheng, J.; Rotondaro, A.; Han, S.-J.; Mo, R.; McStay, K.; Ku, S.; Pal, R.; Kumar, M.; Dirahoui, B.; Yang, B.; Tamweber, F.; Lee, W.-H.; Steigerwalt, M.; Weijtmans, H.; Holt, J.; Black, L.; Samavedam, S.; Turner, M.; Ramani, K.; Lee, D.; Belyansky, M.; Chowdhury, M.; Aime, D.; Min, B.; van Meer, H.; Yin, H.; Chan, K.; Angyal, M.; Zaleski, M.; Ogunsola, O.; Child, C.; Zhuang, L.; Yan, H.; Permanaa, D.; Sleight, J.; Guo, D.; Mittl, S.; Ioannou, D.; Wu, E.; Chudzik, M.; Park, D.-G.; Brown, D.; Luning, S.; Mocuta, D.; Maciejewski, E.; Henson, K.; Leobandung, E.
Source
2009 Symposium on VLSI Technology VLSI Technology, 2009 Symposium on. :140-141 Jun, 2009
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm 2 . V min operation down to 0.6 V in a 16Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by hig-hk/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/µm and V DD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.