학술논문

Silicidation induced strain phenomena in totally silicided (TOSI) gate transistors
Document Type
Conference
Source
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Solid-State Device Research Conference Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European. :427-430 2005
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Silicidation
Capacitive sensors
Tensile stress
Transconductance
Fabrication
Compressive stress
Dielectrics
Performance analysis
Conductivity
Epitaxial growth
Language
ISSN
1930-8876
2378-6558
Abstract
In this paper, we present a detailed analysis of the performance and transport characteristics in totally Ni silicided (TOSI) devices. For two different TOSI integration schemes, we study transconductance variations of TOSI devices with respect to poly-Si gated devices. We find a clear signature of process induced strain related to the total gate silicidation step which depends largely on the integration scheme used for the fabrication of the TOSI devices.