학술논문

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발행년	- (예 : 2010-2015)

전체선택

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

Conference

Ramkaj, Athanasios T.; Steyaert, Michiel S. J.; Tavernier, Filip

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Solid State Circuits Conference (ESSCIRC), ESSCIRC 2019 - IEEE 45th European. :167-170 Sep, 2019

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High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design

Conference

Ramkaj, Athanasios; Perrott, Michael; Haroun, Baher; Murmann, Boris

2023 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2023 IEEE International Symposium on. :1-5 May, 2023

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MULTI-GIGAHERTZ NYQUIST ANALOG-TO-DIGITAL CONVERTERS: ARCHITECTURE AND CIRCUIT INNOVATIONS IN DEEP-SCALED CMOS AND FINFET TECHNOLOGIES.

eBook

RAMKAJ, ATHANASIOS T.

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A 1024-Channel 268-nW/Pixel 36 x 36 mum²/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces

Academic Journal

Jang, Moonhyung; Hays, Maddy; Yu, Wei-Han; Lee, Changuk; Caragiulo, Pietro; Ramkaj, Athanasios T.; Wang, Pingyu; Phillips, A. J.; Vitale, Nicholas; Tandon, Pulkit; Yan, Pumiao; Mak, Pui-In; Chae, Youngcheol; Chichilnisky, E. J.; Murmann, Boris; Muratore, Dante G.

IEEE JOURNAL OF SOLID-STATE CIRCUITS; DEC 29 2023, 14p.

Full Text (IEEE) Web of Science JCR 저널정보 Scopus Find it@PNU

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With < 27 ps / 1 V and < 70 ps / 0.6 V Delay at 5 mV-Sensitivity

Academic Journal

Ramkaj, Athanasios T.; Pelgrom, Marcel J. M.; Steyaert, Michiel S. J.; Tavernier, Filip

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS; AUG 24 2022, 11p.

Full Text (IEEE) Web of Science JCR 저널정보 Scopus Find it@PNU

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity.

Periodical

Ramkaj, Athanasios T.; Pelgrom, Marcel J. M.; Steyaert, Michiel S. J.; Tavernier, Filip

IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Nov2022, Vol. 69 Issue 11, p4404-4414, 11p

Full Text (IEEE) Web of Science JCR 저널정보 Scopus Find it@PNU

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

Academic Journal

Ramkaj, Athanasios T.; Pena Ramos, Juan C.; Pelgrom, Marcel J. M.; Steyaert, Michiel S. J.; Verhelst, Marian; Tavernier, Filip

IEEE JOURNAL OF SOLID-STATE CIRCUITS; JUN 2020, 55 6, p1553-p1564, 12p.

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A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

Academic Journal

Ramkaj, Athanasios T.; Strackx, Maarten; Steyaert, Michiel S. J.; Tavernier, Filip

IEEE JOURNAL OF SOLID-STATE CIRCUITS; JUL 2018, 53 7, p1889-p1901, 13p.

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