부산대학교 도서관

This article proposes and evaluates an architecture for a low-power time-to-digital converter (TDC) with high resolution, optimized for high-rate operation (40 MSa/channel), and integration with analog front end in multichannel readout chips in 130-nm CMOS technology. The converter is based on a three-step architecture. The first step uses a counter and the following ones are based on two types of delay-line (DL) structures. A programmable time amplifier (TA) is used between the second and third steps to reach a final resolution of 24.4 ps in the standard mode of operation. In addition, this architecture uses common continuously stabilized reference blocks that control the channels against the effects of global process, voltage, and temperature (PVT) variations. We also propose a per-channel DL gain correction based on a trimmable block to correct the mismatch effect. The area of the TDC channel is only 0.051 mm2. For a 40-MSa/channel rate, the TDC average power consumption measured per channel is 2.2 mW for a 100% hit occupancy and decreases to 311 $\mu \text{W}$ for the 10% occupancy specified for our main application. The demonstrated compactness and low power consumption fully match our requirements for integration into multichannel front-end chips. The experimental results demonstrate good timing performance over a broad range of operating temperatures (−35 °C and 65 °C), which conforms to our expectations. For example, the measured timing integral nonlinearity (INL) is better than ±1 LSB (±25 ps), and the overall timing precision is better than 21-ps rms.