학술논문

Logic simulation method and system
Document Type
Patent
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Abstract
Correlation between a first node included in a high-level circuit and a second node included in a low-level circuit are determined. The high-level circuit and the low-level circuit are obtained by describing a single logic circuit at two different levels. In logic simulation, the expected value of the first node is “1” and the expected value of the second node is an indefinite value, from which the occurrence of an expected-value error node is detected. In this case, “0” and “1” are assigned to another indefinite-value node that causes the indefinite value of the second node so as to perform logic simulation for each value. And after confirming that the second node has the same value “1” in each logic simulation, the value of the expected-value error node is rewritten with the fixed value “1”. Then, the expected value error between the first and second nodes is corrected, such that the logic simulation can be continuously executed.