학술논문
Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O with Low-Voltage Biased NBL Isolation Ring in a 0.18-μm BCD Technology
Document Type
Article
Author
Source
In: IEEE Transactions on Electron Devices . (IEEE Transactions on Electron Devices, 1 March 2024, 71(3):2224-2227)
Subject
Language
English
ISSN
15579646
00189383
00189383