학술논문

Cascaded SiC JFET Topology for High-Voltage Solid-State Circuit Breaker Applications
Document Type
Periodical
Source
IEEE Transactions on Industry Applications IEEE Trans. on Ind. Applicat. Industry Applications, IEEE Transactions on. 59(2):2326-2339 Apr, 2023
Subject
Power, Energy and Industry Applications
Signal Processing and Analysis
Fields, Waves and Electromagnetics
Components, Circuits, Devices and Systems
JFETs
Silicon carbide
Topology
Logic gates
MOSFET
Switches
Capacitors
DC-circuit breaker
junction field-effect transistors (JFETs)
medium voltage direct current (MVDC)
passive voltage balancing
pulse power
solid-state circuit breaker (SSCB)
silicon carbide (SiC)
super-cascode
wide bandgap
Language
ISSN
0093-9994
1939-9367
Abstract
With evolving landscape of direct current (DC) power transmission and distribution, a reliable and fast protection against faults is critical. High performance DC solid-state circuit breakers (SSCBs) can be designed using silicon carbide (SiC) junction field-effect transistors (JFETs), which utilize the device's intrinsic normally-ON characteristic and low ON-resistance. However, for SSCB that require high-voltage (HV) blocking capability, a proper number of JFETs need to be connected in series to achieve the desired voltage blocking rating. It has been conventional to add a controlling normally-OFF transistor, such a metal-oxide-semiconductor field-effect transistor (MOSFET), resulting in a circuit with normally-OFF behavior. However, disparities both in the voltage rating and in the ON-resistance between MOSFETs and JFETs tend to complicate the circuit design, and physically, they may lead to serious localized thermal stresses. A significant challenge remains with ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage as it is crucial to prevent permanent damages from over-voltage stresses. Therefore, this article presents a new switch topology, in which a cascaded JFET configuration is operated without using a control MOSFET or other added control device. The dynamic voltage balancing network to synchronize both the JFETs' turn ON and OFF intervals is described analytically. Moreover, a novel static voltage balancing network is proposed to establish equal sharing of the total blocking voltage across the series connection of JFETs while maintaining low power loss.