부산대학교 도서관

A two-phase chip performance prediction flow is presented to avoid severe costumer return, reduce power consumption, and mitigate yield loss. In phase I, we first predict the initial value of minimum operating voltage (V min ). In phase II, we predict the bin for each chip in order to apply different guard bands. Experiments on 851 advanced 7nm mobile chips show that predicted V min is larger than actual V min for all chips to avoid customer return. Also, power consumption is reduced by 2.69%. Yield loss is mitigated by up to 5.05% when our V min requirement is 1.20 scaled V min . To implement our flow, we only need to spend a little more runtime compared to the conventional flow. While the runtime of our flow is still short, we can save the long time of measuring V min for every chip.