부산대학교 도서관

A 0.7-pJ/bit, 8.5-Gb/s/link inductive coupling interchip wireless communication interface for a 3D- stacked static-random access memory (SRAM) has been developed in a 7-nm FinFET process. A new physical placement method that allows coils to be placed over off-the-shelf SRAM macros with small magnetic field attenuation, together with the use of synchronous communication using Manchester encoding and a clocked comparator to enable the detection of small-swing signals, achieves a 26% reduction in SRAM die area compared to through-silicon via (TSV)-based stacking. Interchip communication at 0.7 pJ/bit, 8.5 Gb/s/link was confirmed using test chips. A 4-hi 3D- stacked SRAM module using the proposed interface achieves a 1.2-TB/s/mm 2 area efficiency, representing a two orders-of-magnitude improvement over the state-of-the-art 3D- stacked SRAM.