부산대학교 도서관

A novel pulse-width modulation (PWM) architecture for all-digital transmitters (ADT) that achieves good in-band and out-band performance with a very low ratio between the modulated signal frequency and the carrier frequency is presented in this paper. The proposed scheme reduces the harmonics leaving only those corresponding to multiples of the carrier frequency, overcoming the spectral limitations of other PWM implementations and relaxing the filter requirements. The binary signal is obtained using a table-based approach with very low computational complexity, mapping the complex I/Q baseband signal to duty cycles of a square wave with low distortion. In addition, a new parallelized noise shaping circuit to reduce the distortion caused by the discretization of the duty-time intervals is presented. The digital radio frequency signal is generated using a high-speed serializer and a standard pulse former. The ADT is simulated under different scenarios to evaluate the influence of time resolution in terms of Adjacent Channel Power Ratio (ACPR) and Error Vector Magnitude (EVM). The transmitter performance is verified by an FPGA implementation using 64-QAM modulated signals, achieving values of ACPR1, ACPR2, and EVM better than −47 dBc, −53 dBc, and −35 dB, respectively, using 64 quantization levels for the PWM signal.