학술논문

TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis
Document Type
Periodical
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 42(7):2423-2427 Jul, 2023
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Codes
Optimization
Task analysis
Pipelines
Field programmable gate arrays
Kernel
Lenses
Field programmable gate arrays (FPGA)
free running optimization
high level synthesis (HLS)
Language
ISSN
0278-0070
1937-4151
Abstract
Streaming applications have become one of the key application domains for high-level synthesis (HLS) tools. For a streaming application, there is a potential to simplify the control logic by regulating each task with a stream of input and output data. This is called free-running optimization. But it is difficult to understand when such optimization can be applied without changing the functionality of the original design. Moreover, it takes a large effort to manually apply the optimization across legacy codes. In this article, we present the TARO framework which automatically applies the free-running optimization on HLS-based streaming applications. TARO simplifies the control logic without degrading the clock frequency or the performance. Experiments on Alveo U250 shows that we can obtain an average of 16% LUT and 45% FF reduction for streaming-based systolic array designs.