학술논문

Runtime Detection of Time-Delay Security Attack in System-an-Chip
Document Type
Conference
Source
2022 15th IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc) Network on Chip Architectures (NoCArc), 2022 15th IEEE/ACM International Workshop on. :1-6 Oct, 2022
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Runtime
Power demand
System performance
Quality of service
Hardware
Real-time systems
Trojan horses
Hardware Trojan (HT)
System-on-Chip(SoC)
Network-on-Chip (NoC)
Language
Abstract
Soft real-time applications, including multimedia, gaming, and smart appliances, rely on specific architectural characteristics to deliver output in a time-constrained fashion. Any violation of application deadlines can lower the Quality-of-Service (QoS). The data sets associated with these applications are distributed over cores that communicate via Network-on-Chip (NoC) in multi-core systems. Accordingly, the response time of such applications depends on the worst-case latency of request/reply packets. A malicious implant such as Hardware Trojan (HT) that initiates a delay-of-service attack can tamper with the system performance. We model an HT that mounts a time-delay attack in the system by violating the path selection strategy used by the adaptive NoC router. Our analysis shows that once activated, the proposed HT increases the packet latency by 17% and degrades the system performance (IPC) by 18% over the Baseline. Furthermore, we propose an HT detection framework that uses packet traffic analysis and path monitoring to localise the HT. Experiment results show that the proposed detection framework exhibits 4.8% less power consumption and 6.4% less area than the existing technique.