부산대학교 도서관

The emergence of cloud computing, machine learning, and artificial intelligence is gradually saturating network workloads, necessitating rapid growth in datacenter bandwidth, which approximately doubles every 3–4 years. New electrical interfaces that demand dramatic increases in SerDes transceiver speed are being developed to support this. This paper presents a power-efficient 224Gb/s-PAM-4 ADC-based receiver in a 5nm CMOS process that targets next generation Ethernet for chip-to-module applications, envisioned to be the first use-case scenario at this data-rate. Doubling the data-rate from the current IEEE 802.3ck and OIF standards at 112Gb/s, while keeping the same modulation - which is desirable for maintaining backward compatibility with 112/56Gb/s electrical and optical PAM-4 standards - requires doubling the bandwidth and lowering both the clock jitter and circuit noise by a factor of two. These new constraints are met by using 1) a hybrid continuous-time linear equalizer (CTLE) incorporating both inductive peaking and source-degeneration [1] 2) heavy bandwidth extension topologies employing several types of inductive peaking, 3) a low-power interleaved ADC and 4) an inductive clock distribution network with jitter filtering.