학술논문
Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors
Document Type
Conference
Author
Lin, Y.; Shen, P.-C.; Su, C.; Chou, A.-S.; Wu, T.; Cheng, C.-C.; Park, J.-H.; Chiu, M.-H.; Lu, A.-Y.; Tang, H.-L.; Tavakoli, M. M.; Pitner, G.; Ji, X.; McGahan, C.; Wang, X.; Cai, Z.; Mao, N.; Wang, J.; Wang, Y.; Tisdale, W.; Ling, X.; Aidala, K. E.; Tung, V.; Li, J.; Zettl, A.; Wu, C.-I.; Guo, Jing; Wang, H.; Bokor, J.; Palacios, T.; Li, L.-J.; Kong, J.
Source
2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :37.2.1-37.2.4 Dec, 2021
Subject
Language
ISSN
2156-017X
Abstract
Two-dimensional (2D) semiconductors are expected to have exceptional properties for ultimately scaled transistors, but forming ohmic contact to them has been challenging, which tremendously limit the transistor performance. In this paper, we review the recent research progress on the elimination of different gap-state pinning effects, including defect-induced gap states (DIGS) and metal-induced gap states (MIGS). Specifically, an oxygen passivation method and a semimetallic contact technology were developed to reduce the DIGS and MIGS, respectively. Based on these approaches, much improved contact resistance and on-state current were observed. Key device metrics were extracted on these high-performance transistors, which reveals future directions for further improving the device performance.