학술논문
A Binary Translation Framework for Automated Hardware Generation
Document Type
Periodical
Author
Source
IEEE Micro Micro, IEEE. 41(4):15-23 Aug, 2021
Subject
Language
ISSN
0272-1732
1937-4143
1937-4143
Abstract
As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework’s capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.