부산대학교 도서관

This article presents a compact $2\times $ time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC’s architecture is based on parallel charge redistribution and separates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm 2 in 16-nm CMOS and supports up to 0.32- $\textrm {V}_{\textrm {pp}}$ signal swing across its differential 100- ${\Omega }$ load. It achieves an SFDR $\geq 37$ dB and an IM $3\leq -45.6$ dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply.