학술논문
A digitally adjustable resistor for path delay characterization in high-frequency microprocessors
Document Type
Conference
Author
Source
2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475) Mixed-signal design Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on. :61-64 2001
Subject
Language
Abstract
Most high-frequency microprocessors have a clock distribution network allowing the manipulation of the clock edges to facilitate silicon debug and path delay characterization. Typically, a particular edge of the clock is skewed using a variable-delay element until a failure occurs. This paper describes a digitally adjustable resistor applied to the construction of such a variable-delay element. The operation of the digitally adjustable resistor is explained. A strategy to choose the control bits for the resistor is also discussed. The proposed variable-delay element can achieve a 1-ps resolution over a 50-ps range in a 180-nm fabrication technology.