부산대학교 도서관

A differential 6.4 Gb/s/pin bidirectional asymmetric memory interface with a fast all-digital clock calibration method is presented. The proposed clock calibration reduces the link training time of the interface compared to the conventional data eye detection by eliminating the need to sweep the receiver clock phase. Instead a scalable synthesized phase-to-digital converter (PDC) is used to measure the offset from the ideal 90° shift while a clock pattern is transmitted. Phase interpolator nonlinearity is compensated in an additional adjustment step in order to minimize the clock centering error. A prototype ASIC which can be configured to act as either a controller or a memory device was fabricated in a 65nm CMOS process and tested. The measured read and write training durations are 3.1 $\mu \text{s}$ and 3.3 $\mu \text{s}$ , respectively. The additional area required for the PDC in each transceiver is 0.004mm 2 .