학술논문

Flexible HLS-Based Implementation of the Karatsuba Multiplier Targeting Homomorphic Encryption Schemes
Document Type
Conference
Source
2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Mixed Design of Integrated Circuits and Systems, 2019 MIXDES - 26th International Conference. :215-220 Jun, 2019
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Power, Energy and Industry Applications
Signal Processing and Analysis
Hardware
Field programmable gate arrays
Encryption
Program processors
Software libraries
High-Level Synthesis
Karatsuba Multiplier
FPGA
Language
Abstract
Custom accelerators for high-precision integer arithmetic are increasingly used in compute-intensive applications, in particular homomorphic encryption schemes. This work seeks to advance a strategy for faster deployment of these accelerators using the process of high-level synthesis (HLS). Insights from existing number theory software libraries and custom hardware accelerators are used to develop a scalable implementation of Karatsuba modular polynomial multiplication. The accelerator generated from this implementation by the high-level synthesis tool Vivado HLS achieves significant speedup over the implementations available in the highly-optimized FLINT software library. This is an important first step towards a larger goal of enabling HLS-based homomorphic encryption in the cloud.