부산대학교 도서관

Digital Front End Reconfiguration is a promising techniques to deploy the concept of Software Defined Radio (SDR). SDR is a radio communication system whose components are implemented by means of software using Universal Software Radio Peripheral (USRP) and GNU Radio. SDR not only provides cheap and flexible multi-standard-terminals for end users, but also offers a physical layer platform where functions are software defined. Dynamic Partial Reconfiguration (DPR) has proved itself in implementing SDR system on Field Programmable Gate Arrays (FPGAs). This work implements the physical layer of Wi-Fi transceiver chain on Xilinx Zynq board supporting DPR flow. Data is modulated via real communication channel using the USRP RF section connected to the FPGA. A new approach is proposed to enable running the DPR flow and USRP application simultaneously on the same FPGA. Bit Error Rate (BER) calculations are evaluated versus the distance for testing the system integrity.